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v cc v cc c az caz1 caz2 v cc v cc c in 0.01 f 0.01 f 0.01 f c in 0.01 f th squelch n.c. 100 ? in- in+ out+ r term r term r l 100 ? out- max3266 max3267 max3264cue max3265cue max3265eue los loss of signal los n.c. r th level n.c. general description the 1.25gbps max3264/MAX3268/max3768 and the 2.5gbps max3265/max3269/max3765 limiting ampli- fiers are designed for gigabit ethernet and fibre channel optical receiver systems. the amplifiers accept a wide range of input voltages and provide constant- level output voltages with controlled edge speeds. additional features include rms power detectors with programmable loss-of-signal (los) indication, an optional squelch function that mutes the data output sig- nal when the input voltage falls below a programmable threshold, and excellent jitter performance. the max3264/max3265/max3765 feature current-mode logic (cml) data outputs that are tolerant of inductive connectors and a 16-pin tssop package, making these circuits ideal for gbic receivers. the MAX3268/ max3269/max3768 feature standards-compliant posi- tive-referenced emitter-coupled logic (pecl) data out- puts and are available in a tiny 10-pin ?ax package that is ideal for small-form-factor (sff) receivers. applications gigabit ethernet optical receivers fibre channel optical receivers system interconnect atm optical receivers features ? +3.0v to +5.5v supply voltage ? low deterministic jitter 14ps (max3264) 11ps (max3265/max3765) ? 150ps (max) edge speed (max3265/max3765) 300ps (max) edge speed (max3264) ? programmable signal-detect function ? choice of cml or pecl output interface ? 10-pin max or 16-pin tssop package max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers ________________________________________________________________ maxim integrated products 1 19-1523; rev 7, 2/06 + denotes lead-free package. * ep = exposed paddle. ** dice are designed to operate from 0c to +70?, but are tested and guaranteed only at t a = +25?. ordering information selector guide appears at end of data sheet. pin configurations appear at end of data sheet. typical operating circuits typical operating circuits continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max3264 cue 0 c to +70 c 16 tssop-ep* max3264cue+ 0 c to +70 c 16 tssop-ep* max3264c/d 0 c to +70 c dice** max3265 cue 0 c to +70 c 16 tssop-ep* max3265cue+ 0 c to +70 c 16 tssop-ep* max3265cub 0 c to +70 c 10 ?ax-ep* max3265cub+ 0 c to +70 c 10 ?ax-ep* max3265eue -40 c to +85 c 16 tssop-ep* max3265eue+ -40 c to +85 c 16 tssop-ep* max3265c/d 0 c to +70 c dice** ordering information continued at end of data sheet. http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (data outputs terminated per figure 1, v cc = +3.0v to +5.5v, t a = 0c to +70c . typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (v cc ) ............................................-0.5v to +6.0v voltage at in+, in- ..........................(v cc - 2.4v) to (v cc + 0.5v) voltage at squelch, caz1, caz2, los, los , th..................................-0.5v to (v cc + 0.5v) voltage at level...................................................-0.5v to +2.0v current into los, los ..........................................-1ma to +9ma differential input voltage (in+ - in-) .....................................2.5v continuous current at cml outputs (out+, out-) ..........................-25ma to +25ma continuous current at pecl outputs (out+, out-) .........50ma continuous power dissipation (t a = +70?) 16-pin tssop (derate 27mw/? above +70?) .........2162mw 10-pin ?ax (derate 20mw/? above +70?) ...........1600mw operating ambient temperature range .............-40? to +85? storage temperature range .............................-55? to +150? processing temperature (dice) .......................................+400? lead temperature (soldering, 10s) .................................+300? deterministic jitter max3265/max3269/max3765 (notes 2, 3) max3265/max3269/max3765 max3264/MAX3268/max3768 max3265/max3269/max3765 max3264/MAX3268/max3768 4.5 8.5 low los deassert level mv r th = 2.5k ? max3264/MAX3268/max3768 (notes 2, 3) parameter min typ max units 10 1200 5 1200 data rate gbps input voltage range mv 14 30 11 25 1.25 2.5 psp-p 15 random jitter 8 ps rms 80 175 300 100 150 80 150 300 data output edge speed 100 150 ps los hysteresis 2.5 4.4 db los assert/deassert time 1 ? 1.20 2.6 2.20 4.8 low los assert level mv conditions max3264/MAX3268/max3768 (notes 2, 4) max3265/max3269/max3765 max3264/MAX3268/max3768 max3265/max3269/max3765 (notes 2, 4) max3264 (note 5) max3265/max3765 (note 6) MAX3268/max3768 (note 5) max3269 (note 6) max3264/MAX3268/max3768 (notes 2, 7) max3265/max3269/max3765 (notes 7, 8) r th = 2.5k ? http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers _______________________________________________________________________________________ 3 electrical characteristics (continued) (data outputs terminated per figure 1, v cc = +3.0v to +5.5v, t a = 0c to +70c . typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter conditions min typ max units max3264/MAX3268/max3768 5.6 9 medium los assert level r th = 7k ? max3265/max3269/max3765 9.9 16 mv max3264/MAX3268/max3768 15 19.8 medium los deassert level r th = 7k ? max3265/max3269/max3765 27 40.5 mv max3264/MAX3268/max3768 9.4 21.6 high los assert level r th = 20k ? max3265/max3269/max3765 18.0 41.5 mv max3264/MAX3268/max3768 35 high los deassert level r th = 20k ? max3265/max3269/max3765 67 mv squelch input current 0 80 400 ? differential input resistance in+ to in- 97 100 103 ? max3264/MAX3268/max3768 150 input-referred noise max3265/max3269/max3765 230 ? rms level = open, r load = 50 ? ? ? MAX3268 39 62 max3269 48 78 max3264 38 62 max3265 50 76 max3765 50 76 output not squelched max3768 39 62 power-supply current figure 2 output squelched max3765 64 90 ma http://
mv v v mv max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 4 _______________________________________________________________________________________ note 1: specifications for input voltage range, los assert/deassert levels, and cml output voltage refer to the total differential peak-to-peak signal applied or measured. pecl output voltages are absolute (single-ended) voltages measured at a single output. note 2: input edge speed is controlled using four-pole, lowpass bessel filters with bandwidth approximately 75% of the maximum data rate. note 3: deterministic jitter is measured with a k28.5 pattern (0011 1110 1011 0000 0101). deterministic jitter is the peak-to-peak deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ansi x3.230, annex a. note 4: random jitter is measured with the minimum input signal applied after filtering with a four-pole, lowpass, bessel filter (fre- quency bandwidth at 75% of the maximum data rate). for fibre channel and gigabit ethernet applications, the peak-to- peak random jitter is 14.1-times the rms random jitter. note 5: input signal applied after a 933mhz bessel filter. note 6: input signal applied after a 1.8ghz bessel filter. note 7: input for los assert/deassert and hysteresis tests is a repeating k28.5 pattern. hysteresis is defined as: 20log (v los-deassert / v los-assert ). note 8: response time to a 10db change in input power. electrical characteristics?max3265eue (data outputs terminated per figure 1, v cc = +3.0v to +5.5v, t a = -40c to +85c . typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 1) conditions data rate gbps 2.5 units min typ max parameter input voltage range mv 10 1200 (notes 2, 3) deterministic jitter ps p-p 11 25 (notes 2, 4) random jitter ps rms 8 (note 6) data output edge speed ps 100 155 (notes 2, 7) los hysteresis db 2.2 4.4 (notes 7, 8) los assert/deassert time ? 1 output resistance (single ended) ? 85 100 115 c az = 0.1? khz 2 c az = open low-frequency cutoff mhz 2 f < 2mhz power-supply rejection ratio db 20 outputs ac-coupled output signal when squelched 20 i los = +1.2ma los output low voltage 0.450 i los = -30? los output high voltage level = gnd, r load = 75 ? 1100 1270 1800 level = open, r load = 50 ? cml output voltage 550 1200 input-referred noise ? rms 230 in+ to in- differential input resistance ? 97 100 103 squelch input current ? 0 80 400 r th = 20k ? high los deassert level mv 67 111 r th = 20k ? high los assert level mv 18.0 41.5 r th = 7k ? medium los deassert level mv 27 43.0 r th = 7k ? medium los assert level mv 9.9 16 r th = 2.5k ? low los deassert level mv 8.5 13.6 r th = 2.5k ? low los assert level mv 2.20 4.8 figure 2 power-supply current ma 50 76 2.4 http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers _______________________________________________________________________________________ 5 0 25 20 15 10 5 30 0 200 400 600 800 1000 1200 max3264/MAX3268/max3768 deterministic jitter vs. input amplitude max3264/5/8/9 toc04 input amplitude (mv) jitter (ps) 0 14 12 10 8 6 2 4 16 0 1020304050 max3264/MAX3268/max3768 random jitter vs. input amplitude max3264/5/8/9 toc05 input amplitude (mv) rms jitter (ps) 300 900 700 500 1300 1100 1500 1700 024681012 output voltage vs. input voltage max3264/5/8/9 toc01a input voltage (mv) output voltage (mv) max3264/MAX3268 max3265/max3269/max3765 3.5 4.0 6.5 6.0 5.5 5.0 4.5 0 10203040506070 max3264 los hysteresis vs. temperature max3264/5/8/9 toc03a temperature (?) los hysteresis (db) r th = 25k ? r th = 7k ? 0 25 20 15 10 5 30 0 200 400 600 800 1000 1200 max3265/max3269/max3765 deterministic jitter vs. input amplitude max3264/5/8/9 toc06 input amplitude (mv) jitter (ps) 0 7 6 5 4 3 1 2 8 0 1020304050 max3265/max3269/max3765 random jitter vs. input amplitude max3264/5/8/9 toc07 input amplitude (mv) rms jitter (ps) v in v out v los loss of signal with squelch max3264/5/8/9 toc08 500ns/div 300mv/div 200ps/div MAX3268/max3768 data output eye diagram (minimum input) max3264/5/8/9 toc09 typical operating characteristics (t a = +25?, unless otherwise noted.) 3.5 4.0 6.5 6.0 5.5 5.0 4.5 -40 -15 10 35 60 85 max3265eue los hysteresis vs. temperature max3264/5/8/9 toc03 temperature ( c) los hysteresis (db) r th = 4.6k ? r th = 16k ? http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 6 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 150mv/div max3265/max3765 data output eye diagram 2.5gbps (maximum input) max3264/5/8/9 toc13 100ps/div 0 25 15 20 10 5 100k 1m 10m 100m 1g power-supply rejection ratio vs. frequency max3264/5/8/9 toc14 frequency (hz) psrr (db) 1.0 3.5 3.0 2.5 1.5 2.0 4.0 0 0.5 1.0 1.5 2.0 3.0 output vswr vs. frequency max3264/5/8/9 toc15 frequency (ghz) vswr 2.5 0 10 5 20 15 35 30 25 40 010 5 1520253035 max3264 loss-of-signal threshold vs. r th max3264/5/8/9 toc18 r th (k ? ) los assert threshold (mv) 0 50 40 30 10 20 60 0102030 51525 max3265/max3765 loss-of-signal threshold vs. r th max3264/5/8/9 toc19 r th (k ? ) los assert threshold (mv) 5 40 45 50 35 30 20 15 10 25 55 1m 100m 10g 10m 1g common-mode rejection ratio vs. frequency max3264/5/8/9 toc20 frequency (hz) cmrr (db) MAX3268/max3768 max3265/max3765 150mv/div max3264 data output eye diagram at 1.25gbps (minimum input) max3264/5/8/9 toc10 200ps/div 50mv/div max3264 data output eye diagram at 1.25gbps (maximum input) max3264/5/8/9 toc11 200ps/div 150mv/div max3265/max3765 data output eye diagram 2.5gbps (minimum input) max3264/5/8/9 toc12 100ps/div http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers _______________________________________________________________________________________ 7 pin description ep ep ground. the exposed paddle must be soldered to the circuit?oard ground for proper thermal performance. exposed paddle 7 output current level. when this pin is not connected, the cml output current is approximately 16ma. when this pin is connected to ground, the output current increases to approximately 20ma. (in the max3265cub/max3765cub, level is internally connected to ground.) 15 squelch input. the squelch function is disabled when squelch is not connected or is set to a ttl low level. when squelch is set to a ttl high level and los is asserted, the data outputs, out+, and out-, are forced to static levels. see sec- tions pecl output buffe r and cml output buffer for more information. (in the max3265/MAX3268/max3269 10-pin ?ax, squelch is not connected. in the max3765/max3768, squelch is internally connected to v cc .) 16 no connection n.c. squelch 10 noninverted loss-of-signal output. los is low when the level of the input signal is above the preset threshold set by the th input. los asserts high when the sig- nal level drops below the threshold. los level 1 offset-correction-loop capacitor. a capacitor connected between this pin and caz2 extends the time constant of the offset correction loop. 2 offset-correction-loop capacitor. a capacitor connected between this pin and caz1 extends the time constant of the offset correction loop. refer to design procedure . caz2 caz1 6 9 inverted loss-of-signal output. los is high when the level of the input signal is above the preset threshold set by the th input. los is asserted low when the signal level drops below the threshold. 8 12 inverted data output 9 13 noninverted data output out+ out- 7, 10 11, 14 supply voltage v cc los 3 5 inverted input signal 5 8 loss-of-signal threshold. a resistor connected from this pin to ground sets the input signal level at which the loss-of-signal (los) output(s) is asserted. refer to typical operating characteristics and design procedure. th in- 2 4 noninverted input signal in+ tssop function max name gnd 1, 4 3, 6 supply ground pin http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 8 _______________________________________________________________________________________ (a) max3264/max3265/max3765 with 50 ? termination v cc 100 ? 100 ? 100 ? r term 100 ? 2 x r load 100 ? c out c out c out c out v cc (b) max3264/max3265/max3765 with 75 ? termination v cc 100 ? 100 ? 300 ? r term 300 ? 2 x r load 150 ? v cc (c) MAX3268/max3269/max3768 output termination v cc v cc - 2v out- out+ 50 ? r term 50 ? max3264 max3265 max3765 max3264 max3265 max3765 MAX3268 max3269 max3768 figure 1. data output termination http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers _______________________________________________________________________________________ 9 (a) cml supply current (i cc ) v cc i cc i cc v cc out+ open open out- i out 100 ? r th 2.5k ? 100 ? control squelch level max3264cue: open max3265cue: open max3265cub: gnd (internal) max3765cub: v cc (internal) (b) pecl supply current (i cc ) r th 2.5k ? max3264 max3265 max3765 MAX3268 max3269 max3768 max3264cue: open max3265cue: open max3265cub: gnd (internal) max3765cub: gnd (internal) figure 2. power-supply current measurement http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 10 ______________________________________________________________________________________ _______________detailed description figure 3 is a functional diagram of the max3264/ max3265/MAX3268/max3269/max3765/max3768 lim- iting amplifiers. a linear input buffer drives a multistage limiting amplifier and an rms power-detection circuit. offset correction with lowpass filtering ensures low deterministic jitter. the output buffer produces a limited output signal. the max3264/max3265/max3765 pro- duce a cml output, while the MAX3268/max3269/ max3768 produce a pecl-compatible output signal. schematics of these input/output circuits are shown in figures 4 through 7. rms power detect with loss-of-signal indicator an rms power detector looks at the signal from the input buffer and compares it to a threshold set by the th resistor (see typical operating characteristics for appropriate resistor values). the signal-detect informa- tion is provided to the los outputs, which are internally terminated with 8k ? (max3265/max3269/max3765) or 16k ? (max3264/MAX3268/max3768) pullup resistors. the los outputs meet ttl voltage specifications when loaded with a resistor 4.7k ? . control gain v cc th v cc r los = 8k ? (max3265/max3269/max3765) r los = 16k ? (max3264/MAX3268/max3768) los r los r los los out+ out- squelch level input buffer caz1 caz2 offset correction 100 ? in+ in- max3264 max3265 MAX3268 max3269 max3765 max3768 low- pass 100pf total gain = 55db (max3264/MAX3268/max3768) total gain = 49db (max3265/max3269/max3765) power detect with comparator output buffer ttl ttl figure 3. functional diagram http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers ______________________________________________________________________________________ 11 input buffer the input buffer is designed to accept input signals from the max3266/max3267 transimpedance ampli- fiers. the input buffer provides a 100 ? input imped- ance between in+ and in-. input vswr is typically less than 2.0 for frequencies less than 2ghz. dc-coupling the inputs is not recommended; this prevents the dc offset-correction circuitry from functioning properly. gain stage and offset correction the limiting amplifier provides approximately 55db (max3264/MAX3268 /max3768) or 49db (max3265/ max3269/max3765) of gain. this large gain makes the amplifier susceptible to small dc offsets in the input sig- nal. dc offsets as low as 1mv reduce the accuracy of the power-detection circuit and may cause deterministic jitter. a low-frequency feedback loop is integrated into the limiting amplifier to reduce input offset, typically to less than 100?. an external capacitor connected between caz1 and caz2, in parallel with internal capacitance, determines the time constant of the offset-correction circuit. the off- set-correction circuit requires an average data-input mark density of 50% to prevent an increase in duty- cycle distortion and to ensure low deterministic jitter. cml output buffer the max3264/max3265/max3765 cml output circuits (figure 7) provide high tolerance to impedance mis- matches and inductive connectors. the output current can be set to two levels. when the level pin is left unconnected, output current is approximately 16ma. connecting level to ground sets the output current to approximately 20ma. the squelch function is enabled when the squelch pin is set to a ttl-high level or connected to v cc . the squelch function holds out+ and out- at a static volt- age whenever the input signal power drops below the loss-of-signal threshold. in the 10-pin ?ax package of the max3265/MAX3268/max3269, the squelch func- tion is left internally unconnected. in the max3765/ max3768, the squelch function is always enabled by internally connecting it to v cc . squelch operation for the max3264/max3265 is described in table 1. internal input/output schematics in+ in- 110 ? gnd esd structures v cc 500 ? 500 ? 0.25pf 0.25pf figure 4. input circuit gnd r t = 8k ? (max3265/max3269/max3765) r t = 16k ? (max3264/MAX3268/max3768) esd structure v cc los r t figure 5. los output circuit table 1. level pin voltage when squelched out- out+ open v cc - 100mv v cc gnd v cc - 100mv v cc - 100mv http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 12 ______________________________________________________________________________________ the buffer? output impedance is determined by the par- allel combination of internal and external pullup resistors, which are chosen to match the impedance of the trans- mission line (figure 1). the output buffer can be ac- or dc-coupled to the load. pecl output buffer the MAX3268/max3269/max3768 offer an industry- standard pecl output. the pecl outputs should be terminated to v cc - 2v. figure 6 shows the pecl out- put circuit. the squelch function forces out+ to a high level and out- to a low level when the input is below the programmed los threshold. in the 10-pin ?ax, squelch is left unconnected. __________________design procedure program the los assert threshold the loss-of-signal threshold is programmed by external resistor r th . see the los threshold vs. r th graph in the typical operating characteristics. select the coupling capacitors the coupling capacitors (c in, c out ) should be select- ed to minimize the receiver? deterministic jitter. jitter is minimized when the input low-frequency cutoff (f in ) is placed at a low frequency: f in = 1 / [2 (50)(c)] for fibre channel, gigabit ethernet, or other applica- tions using 8b/10b data coding, select (c in, c out ) 0.01?, which provides f in < 320khz. for atm/sonet or other applications using scrambled nrz data, select (c in ,c out ) 0.1?, which provides f in < 32khz. select the offset-correction capacitor (max3264/max3265 tssop only) to maintain stability, it is important to keep a one- decade separation between f in and the low-frequency cutoff (f oc ) associated with the dc-offset-correction cir- cuit. f oc = 75 / [2 60k (c az + 100pf)] = 200 x 10 -6 / (c az + 100pf) for fibre channel, gigabit ethernet, or other applica- tions using 8b/10b data coding, leave pins caz1, and caz2 open (f oc = 2mhz). for atm/sonet or other applications using scrambled nrz data, select c az 0.1?, which typically provides f oc = 2khz. gnd esd structures v cc out- out+ figure 6. pecl output circuit gnd level esd structures v cc 100 ? 100 ? out- out+ figure 7. cml output circuit http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers ______________________________________________________________________________________ 13 applications information optical hysteresis in an optical receiver, the electrical power change at the limiting amplifier is 2x the optical power change. as an example, if a receiver? optical input power (x) increases by a factor of two, and the preamplifier is lin- ear, then the voltage input to the limiting amplifier also increases by a factor of two. the optical power change is 10log(2x / x) = 10log(2) = +3db. at the limiting amplifier, the electrical power change is: the max3264/max3265/MAX3268/max3269/max3765s typical voltage hysteresis is 4.4db. this provides an opti- cal hysteresis of 2.2db. gbic loss of signal in a gbic application, the gbic? los output must be high impedance when v cc_ module = gnd. figure 8 shows the recommended circuit to maintain high impedance. esd protection diodes on the max3264/ max3265/MAX3268/max3269/max3765/max3768 los outputs can be turned on when v cc_ host > v cc_ module. pecl terminations the standard pecl termination (50 ? to v cc - 2v) is recommended for best performance and output char- acteristics (see figure 1). the data outputs operate at high speed and should always drive transmission lines with matched, balanced terminations. figure 9 shows an alternate method for terminating the data outputs. the technique provides approximately 8ma dc bias current, with a 45 ? ac load, for the out- put termination. this technique is useful for viewing the output on an oscilloscope or changing the pecl refer- ence voltage. wire bonding dice for high current density and reliable operation, the max3264/max3265/MAX3268/max3269 use gold met- alization. make connections to the dice with gold wire only, and use ballbonding techniques (wedge bonding is not recommended). die-pad size is 4-mils square, with a 6-mil pitch. die thickness is 15 mils (0.375mm). 10log 2v / r v/ r 10log(2 ) 20log(2) 6db in 2 in in 2 in 2 () ===+ v cc_ module gbic module v cc_ host 4.7k ? host los general- purpose npn max3264 max3265 MAX3268 max3269 max3765 max3768 figure 8. recommended gbic los circuit 470 ? driving 50 ? to ground 470 ? 50 ? 50 ? out+ out- MAX3268 max3269 max3768 figure 9. alternative pecl termination http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 14 ______________________________________________________________________________________ typical operating circuits (continued) 50 ? 50 ? r th v cc v cc c in 0.01 f c in 0.01 f th 100 ? in- in+ out+ out- max3266 max3267 MAX3268cub max3269cub max3768cub los signal detect v cc - 2v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 caz1 n.c. squelch v cc out+ out- v cc los los top view max3264 max3265 tssop caz2 gnd gnd in+ in- level th 1 2 3 4 5 10 9 8 7 6 v cc out+ out- v cc gnd in- in+ gnd max3265 MAX3268 max3269 max3765 max3768 max los th note: exposed paddle is ground. pin configurations ordering information (continued) part temp range pin-package MAX3268 cub 0 c to +70 c 10 ?ax-ep* MAX3268cub+ 0 c to +70 c 10 ?ax-ep* MAX3268c/d 0 c to +70 c dice** max3269 cub 0 c to +70 c 10 ?ax-ep* max3269cub+ 0 c to +70 c 10 ?ax-ep* max3269c/d 0 c to +70 c dice** max3765 cub 0 c to +70 c 10 ?ax-ep* max3765cub+ 0 c to +70 c 10 ?ax-ep* max3768 cub 0 c to +70 c 10 ?ax-ep* max3768cub+ 0 c to +70 c 10 ?ax-ep* + denotes lead-free package. * ep = exposed paddle. ** dice are designed to operate from 0c to +70?, but are tested and guaranteed only at t a = +25?. http://
max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers ______________________________________________________________________________________ 15 chip topographies in- gnd level 0.061" (1.55mm) 0.061" (1.55mm) th n.c. los squelch v cc out+ out- v cc los caz1 n.c. in+ caz2 gnd in- gnd 0.061" (1.55mm) 0.061" (1.55mm) th n.c. los squelch v cc out+ out- v cc los caz1 n.c. in+ caz2 gnd max3264/max3265/max3765 MAX3268/max3269/max3768 max3264/max3265/max3765 transistor count: 726 MAX3268/max3269/max3768 transistor count: 728 substrate connected to gnd selector guide * level pin grounded cml 2.5 max3765 10 ?ax-ep enabled maximum* pecl 2.5 max3269 cml 2.5 max3265 1.25 1.25 data rate (gbps) 10 ?ax-ep disabled 10 ?ax-ep disabled disabled selectable selectable squelch function 10 ?ax-ep 16 tssop-ep 16 tssop-ep pin- package n/a maximum* n/a selectable selectable cml output level pecl MAX3268 cml max3264 output part pecl 1.25 max3768 10 ?ax-ep enabled n/a http://
10lumax.eps package outline, 10l umax/usop 1 1 21-0061 rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1 max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers 16 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) http://
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 17 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. tssop 4.4mm body.eps e 1 1 21-0108 package outline, tssop, 4.40 mm body, exposed pad xx xx max3264/max3265/MAX3268/max3269/max3765/max3768 +3.0v to +5.5v, 1.25gbps/2.5gbps limiting amplifiers package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) http://

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